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Electrical Specifications
Table 2.2 Operating Conditions
MR4A08B
Parameter
Power supply voltage
Write inhibit voltage
Input high voltage
Input low voltage
Temperature under bias
MR4A08B (Commercial)
MR4A08BC (Industrial)
MR4A08BM (AEC-Q100 Grade 1) iv
Symbol
V DD
V WI
V IH
V IL
T A
Min
3.0 i
2.5
2.2
-0.5 iii
0
-40
-40
Typical
3.3
2.7
-
-
Max
3.6
3.0 i
V DD + 0.3 ii
0.8
70
85
125
Unit
V
V
V
V
°C
i
ii
iii
iv
There is a 2 ms startup time once V DD exceeds V DD, (min). See Power Up and Power Down Sequencing below.
V IH (max) = V DD + 0.3 V DC ; V IH (max) = V DD + 2.0 V AC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
V IL (min) = -0.5 V DC ; V IL (min) = -2.0 V AC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life)
Power Up and Power Down Sequencing
MRAM is protected from write operations whenever V DD is less than V WI . As soon as V DD exceeds V DD (min),
there is a startup time of 2 ms before read or write operations can start. This time allows memory power
supplies to stabilize.
The E and W control signals should track V DD on power up to V DD - 0.2 V or V IH (whichever is lower) and re-
main high for the startup time. In most systems, this means that these signals should be pulled up with a
resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and
W should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where V DD goes below V WI , writes are protected and a startup time must be
observed when power returns above V DD (min).
Figure 2.1 Power Up and Power Down Diagram
V WIDD
V DD
STARTUP
2 ms
BROWNOUT or POWER LOSS
2 ms
RECOVER
READ/WRITE
INHIBITED
NORMAL
OPERATION
READ/WRITE
INHIBITED
NORMAL
OPERATION
V IH
V IH
E
W
Copyright ? Everspin Technologies 2013
5
MR4A08B Rev. 6 9/2013
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